% 8" (!"beagle,beaglev-aheadthead,th1520 &BeagleV Aheadcpus ,-cpu@0thead,c910riscv?cpu Krv64imafdcUrv64i(dimafdczicntrzicsrzifenceizihpmy}@@ riscv,sv39interrupt-controllerriscv,cpu-intccpu@1thead,c910riscv?cpu Krv64imafdcUrv64i(dimafdczicntrzicsrzifenceizihpmy}@@ riscv,sv39interrupt-controllerriscv,cpu-intccpu@2thead,c910riscv?cpu Krv64imafdcUrv64i(dimafdczicntrzicsrzifenceizihpmy}@@ riscv,sv39interrupt-controllerriscv,cpu-intccpu@3thead,c910riscv?cpu Krv64imafdcUrv64i(dimafdczicntrzicsrzifenceizihpmy}@@ riscv,sv39interrupt-controllerriscv,cpu-intcl2-cachecache@+oscillator fixed-clock9osc_24mLYn632k-oscillator fixed-clock9osc_32kLYapb-clk-clock fixed-clock9apb_clkLY uart-sclk-clock fixed-clock 9uart_sclkLYsdhci-clock fixed-clockY = 9sdhci_clkLsoc simple-busi zinterrupt-controller@ffd8000000"thead,th1520-plicthead,c900-plicy@         timer@ffdc000000$thead,th1520-clintthead,c900-clinty@serial@ffe7014000snps,dw-apb-uarty@$okaymmc@ffe7080000thead,th1520-dwcmshcy>coreokay =!)mmc@ffe7090000thead,th1520-dwcmshcy @coreokay =mmc@ffe70a0000thead,th1520-dwcmshcy Gcore disabledserial@ffe7f00000snps,dw-apb-uarty% disabledserial@ffe7f04000snps,dw-apb-uarty@' disabledgpio@ffe7f34000snps,dw-apb-gpioy@ gpio-controller@0snps,dw-apb-gpio-port/?K y:gpio@ffe7f38000snps,dw-apb-gpioy gpio-controller@0snps,dw-apb-gpio-port/?K y;gpio@ffec005000snps,dw-apb-gpioyP gpio-controller@0snps,dw-apb-gpio-port/?K y8gpio@ffec006000snps,dw-apb-gpioy` gpio-controller@0snps,dw-apb-gpio-port/?K y9serial@ffec010000snps,dw-apb-uarty@& disableddma-controller@ffefc00000snps,axi-dma-1.01ay core-clkcfgr-clkR]jzokaytimer@ffefc32000snps,dw-apb-timery  timer disabledtimer@ffefc32014snps,dw-apb-timery  timer disabledtimer@ffefc32028snps,dw-apb-timery ( timer disabledtimer@ffefc3203csnps,dw-apb-timery < timer disabledserial@fff7f08000snps,dw-apb-uarty@( disabledserial@fff7f0c000snps,dw-apb-uarty@) disabledtimer@ffffc33000snps,dw-apb-timery0 timer disabledtimer@ffffc33014snps,dw-apb-timery0 timer disabledtimer@ffffc33028snps,dw-apb-timery0( timer disabledtimer@ffffc3303csnps,dw-apb-timery0< timer disabledgpio@fffff41000snps,dw-apb-gpioy gpio-controller@0snps,dw-apb-gpio-port/?K yLgpio@fffff52000snps,dw-apb-gpioy  gpio-controller@0snps,dw-apb-gpio-port/?K y7aliases/soc/gpio@ffec005000/soc/gpio@ffec006000/soc/gpio@ffe7f34000/soc/gpio@ffe7f38000/soc/serial@ffe7014000/soc/serial@ffe7f00000/soc/serial@ffec010000/soc/serial@ffe7f04000/soc/serial@fff7f08000/soc/serial@fff7f0c000chosenserial0:115200n8memory@0?memoryy compatible#address-cells#size-cellsmodeltimebase-frequencydevice_typeriscv,isariscv,isa-baseriscv,isa-extensionsregi-cache-block-sizei-cache-sizei-cache-setsd-cache-block-sized-cache-sized-cache-setsnext-level-cachemmu-typeinterrupt-controller#interrupt-cellsphandlecache-levelcache-unifiedclock-output-names#clock-cellsclock-frequencyinterrupt-parentdma-noncoherentrangesinterrupts-extendedriscv,ndevinterruptsclocksreg-shiftreg-io-widthstatusclock-namesbus-widthmax-frequencymmc-hs400-1_8vnon-removableno-sdiono-sdgpio-controller#gpio-cellsngpios#dma-cellsdma-channelssnps,block-sizesnps,prioritysnps,dma-masterssnps,data-widthsnps,axi-max-burst-lengpio0gpio1gpio2gpio3serial0serial1serial2serial3serial4serial5stdout-path